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Cryptographic Hardware and Embedded Systems – CHES 2005
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Editor(s):
Josyula R. Rao
,
Berk Sunar
Publication date
(Print):
2005
Publisher:
Springer Berlin Heidelberg
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ISBN (Print):
978-3-540-28474-1
ISBN (Electronic):
978-3-540-31940-5
Publication date (Print):
2005
DOI:
10.1007/11545262
SO-VID:
e3bba9f1-2c6e-4bfd-b012-cb0ee9aae72e
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Book chapters
pp. 383
The “Backend Duplication” Method
pp. 30
A Stochastic Model for Differential Side Channel Cryptanalysis
pp. 412
Efficient Hardware for the Tate Pairing Calculation in Characteristic Three
pp. 75
Energy-Efficient Software Implementation of Long Integer Modular Arithmetic
pp. 157
Successfully Attacking Masked AES Hardware Implementations
pp. 172
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
pp. 187
Masking at Gate Level in the Presence of Glitches
pp. 293
On Second-Order Differential Power Analysis
pp. 309
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
pp. 339
Data Remanence in Flash Memory Devices
pp. 427
AES on FPGA from the Fastest to the Smallest
pp. 441
A Very Compact S-Box for AES
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